1. Field of the Invention
This invention relates to a power conversion methodology and circuit for a tapped-inductor buck topology that in general relates to systems and methods for power conversion, and in particular to a system and method for power conversion that takes advantage of an integrated magnetic auxiliary reset winding and intrinsic leakage inductance in the coupled inductors of a tapped-inductor buck converter to reuse the energy in the circuit to help power a simple MOSFET lower switch gate-drive circuit which improves the overall efficiency of the converter, while simultaneously simplifying the circuit design in multiphase power conversion for voltage regulation (VR) technologies.
2. Description of the Related Art
High performance electronics today are demanding higher performance power delivery than in previous years. As an example, high performance microprocessors are forcing power converters to supply voltages at 1 Volt (V) and below and deliver power over 100 Watts (W). This translates to delivered currents in excess of 100 amps. Moreover, the small space allocated on motherboards and other printed circuit boards, along with the thermal considerations at the system level, require the voltage regulators to be highly efficient, have low noise, and maintain a very small form factor. This trend is requiring advancements in power conversion technology which not only necessitate using advanced componentry but sophisticated topologies and circuit design in power conversion as well.
Today, input voltages for many non-isolated power converter technologies in high performance microelectronics is 12V (though 48V input voltages are becoming more common as well). Use of lower input voltages than 12V increases conduction loss and is used less frequently. Use of higher input voltages often results in more complex power distribution and is typically more costly. As an example, 48V input converters usually require the addition of a 48V to 12V first stage converter followed by a second stage 12V to low voltage (e.g. 1V to 2V) converter to optimize the efficiency and performance of the field effect transistors (FETs) typically used in such circuits. To maximize efficiency, space, and cost, most non-isolated DC-to-DC converters today are based upon the simple Buck topology.
FIG. 1 shows a schematic of a buck converter circuit 100. The buck converter circuit 100 has a first main switch 104 coupled to an input signal 102 and a second main switch 106. Typically, the first and second main switches 104 and 106 are field effect transistors (FETs) such as metal oxide field effect transistors (MOSFETs), each having gates 114 and 116, respectively. As illustrated in FIG. 1, the switches 104 and 106 can be individual switches or can be combined in a single device. In combination with the other circuit elements illustrated, the switches are used to step down the higher 12V input to a lower voltagexe2x80x94typically below 2V.
An inductor 108 is connected between the output Vout 112 and the junction of the two switches 104 and 106 (labeled xe2x80x9cAxe2x80x9d in FIG. 1). The drain of the first (upper) switch 104 is electrically connected to Vin 102, which is typically 12 volts, while the source of the lower switch 106 is electrically connected to ground 122 with one end of the inductor 108 between them. The output 112 includes a capacitor 110 connected between inductor 108 and ground 122 for storage of charge and filtering. A load (not shown) is connected to the output 112 where power is delivered.
FIG. 2 is a timing diagram further illustrating the operation of buck converter 100. When the upper switch 104 is on (VG104 at time t1 to t2), the gate voltage 116 on lower switch 106 (VG106 at time t1 to t2) is at a low voltage, turning off lower switch 106. Because the upper FET 104 is on, the voltage at node A is high (VA at time t1). A controller (not shown) drives the two switches 104 and 106. The control of switches 104 and 106 is timed so that each switch is (ideally) off when the other switch is on. However, FET switches 104, 106 cannot turn on and off instantaneously in a perfectly timed manner. Additionally, parasitic effects of the FET switches 104, 106, such as the substrate diode and the drain-to-source capacitance, contribute to the non-ideal switching. What occurs is the substrate diode of the lower switch is brought into conduction due to the upper transistor switch not instantaneously responding to the inductor current with the lower switch turned off. Because of these problems, large voltage and current spikes occur across the FET switches 104 and 106, particularly the upper FET switch 104, which results in increased losses through the FETs 104 and 106 [P104/106 from t1 to t2] and can cause potential damage to the FETs themselves. Also occurring at time t1, the current through upper FET 104 spikes [IS104 at time t1] due to the substrate diode of lower FET 106 continuing to conduct even after the gate voltage 116 of FET 106 is low (e.g. the FET is turned off). This surge current continues until the substrate diode of FET 106 is completely off. The current through upper FET 104 then increases until time t2 when the gate voltage [VG104 at time t2] goes low and another power spike occurs at time t2. During the on cycle of the upper FET 104 power is being delivered to the output. This can be seen by noticing the inductor current I108 increases until time t2 when upper FET switch 104 is turned off. During the conduction cycle of the lower FET 106, current continues to flow through inductor 108 from time t2 to time t3. The cycle repeats itself starting at time t3.
The asymmetric behavior of the current through inductor 108 in a buck converter results in a large ripple voltage, which may not be conducive to proper electronic device operation. Thus, to mitigate this problem, designers typically use multiple phases of the buck topology to reduce output voltage ripple and current through each FET. A multi-phase buck converter has two or more converters, similar to buck converter 100, operating synchronously through a main controller circuit to deliver power to a common load. Multi-phase operation helps reduce output voltage ripple while sharing the current equally through each phase of the converter.
Though the buck converter 100 is simple and elegant it has its drawbacks for high current low voltage power delivery. The duty cycle for the buck converter is small and may be approximated by the relation D≈Vo/Vin, resulting in very short on times for the upper FET switch 104 as illustrated above. Because of this short duty cycle the rising and falling inductor currents are asymmetric resulting in poor transient response. This is because the declining rate of change of current of the inductor 108 is slow relative to the rising speed. Additionally, the turn-off current for the upper FET switch 104 is equivalent to the peak output current, which results in very high losses in the upper FET during the switching, cycles (e.g. when the upper FET switch is on). Some of these problems may be mitigated through modifications of the standard buck topology as will be shown.
FIG. 3 is a diagram showing another converter topology known as a tapped-inductor buck converter 300. The tapped-inductor buck converter 300 uses a coupled input inductor 304 and output inductor 310 between the upper FET 306 and the input voltage source 302 with the inductors coupling magnetically to each other. Throughout this description coupled inductors will be shown with the dot convention . . . one type of dot will show coupling between one set of coupling, etc. Instead of the drain of the upper FET 306 connecting to the input voltage 302 the input inductor 304 is connected between it and the input 302. As shown in FIG. 3, tapped-inductor buck converter circuit 300 has input voltage source VIN 302 connected to inductor 304 which is connected to upper FET 306 and magnetically coupled to output inductor 310 such that when the upper FET 306 is off, the magnetic flux through the input inductor 304 induces a current in output inductor 310 which flows into the output VOUT 312. VOUT 312 is coupled to ground via capacitor 318. Also note, the arrangement shown in circuit 300, although not literally a xe2x80x98tapped-inductorxe2x80x99, is a derivative of a tapped-inductor configuration wherein the switch 306 has been moved from the input side VIN 302 to the side connecting to the output inductor 310. This configuration is more conducive to driving upper FET 306 with lower voltage levels than in an actual tapped-inductor configuration. FETs 306 and 308 are controlled by a control signal applied to gates 316 and 314.
FIG. 4 is a timing diagram illustrating the operation of the tapped-inductor buck converter 300. At time t1 to t2, when upper FET 306 is on VG306 is positive, lower FET 308 is off. The voltage at node A goes high, i.e., VA(t1 to t2)=Vout+(Vinxe2x88x92Vout)/n, where n is the turns ratio (n=[N304+N310]/N310, N represents the number of turns on each winding.) Current through upper FET 306 at time t1 is initially high due to the conduction in the substrate diode of lower FET 308 until it fully shuts off. The current continues to rise until time t2 when the upper FET 306 is turned off. The duty cycle, D=[nVout]/[Vin+(nxe2x88x921)Vout], is typically larger for the tapped-inductor buck converter 300 than the standard buck converter 100 and can be modified by changing the inductor turns ratios, n, as the input and output voltages are changed to optimize the switching and conduction losses in the FETs 306 and 308. This is an advantage over a standard buck converter 100. The current through output inductor 310, I310, also shows that the rate of change of current can be made approximately the same in both the switching and conduction cycles of the converter by appropriate selection of n. This results in a better transient response over the standard buck converter.
As explained above, the tapped-inductor buck converter 300 typically has a larger duty cycle and a more balanced inductor current through the full switching cycle. Additionally, the losses through the upper FET 306 and lower FET 308 are less due to the reduced peak currents through the upper FET 306 and the shorter conduction time through the lower FET 308. However, the tapped-inductor buck converter 300 has some drawbacks as well. First, when the upper FET switch 306 is turned off, the voltage across the input inductor 304 reverses, resulting in a large voltage spike across the upper FET 306. This voltage is typically higher even than in a standard buck converter due to the addition of the input coupled inductor 310. Additionally, the imperfect coupling between the input 304 and output inductors 310 results in a leakage inductance which increases this voltage spike even further. This voltage spike can destroy the upper FET 306 if not kept in check and results in increased losses through the upper FET 306 as well. Use of integrated planar magnetics (e.g. magnetic windings imbedded within the planes of the printed circuit board) helps to reduce the leakage inductance but the leakage inductance is still typically quite high due to lack of the ability to perfectly couple inductors 304 and 310. The other problem is timing and control of the upper FET switch 306. FET controllers and gate drivers are often used to control the upper and lower FET switches of multi-phase buck converters. Such devices are used to synchronize the turn-on and turn-off times of the FETs 306 and 308 to minimize losses. However, the devices are often expensive, can have fairly slow slew-rates, do not adjust the timing perfectly between the upper and lower FETs well enough, and often put out low gate drive voltages which can impact conduction losses in the FETxe2x80x94particularly the lower FET 308. If a FET controller is imperfect and poor synchronization occurs between the turning off of the upper and lower FETs 306 and 308, losses will be increased in both devices resulting in a less efficient converter.
There have been a number of circuits and methods proposed to solve some of these problems intrinsic to the tapped-inductor buck and standard buck converters. However, these methods have typically only addressed portions of the overall problem which have limited the use of tapped-inductor buck converters to date. What is needed is a method and circuit technique which uses the advantages of the multi-phase tapped inductor buck converter and makes use of some of the facets of the design, such as leakage inductance, to improve efficiency, form factor, and gate-drive control in an integrated manner to result in a simpler, more elegant power conversion methodology and topology than exists today. The present invention accomplishes this goal.
The present invention is described as a method and apparatus for regulating voltage. The apparatus comprises an input inductor having an input inductor first terminal coupled to an input signal and an input inductor second terminal; a first switch, having a first switch first terminal coupled to the input inductor second terminal, a first switch second terminal, and a first switch control terminal coupled to a control signal; a second switch, having a second switch first terminal coupled to the first switch second terminal, a second switch second terminal coupled to ground, and a second switch control terminal; an output inductor magnetically coupled to the input inductor according to a first coupling coefficient loosely coupled, the output inductor having an output inductor first terminal coupled to the second switch first terminal, and an output inductor second terminal coupled to an output signal; an auxiliary inductor having a first auxiliary inductor terminal coupled to ground via a first capacitor and a second auxiliary inductor terminal coupled to the second switch control terminal via a resistor, wherein the auxiliary inductor is magnetically coupled to the input inductor according to a second coupling coefficient higher than the first coupling coefficient; and a third switch, having a third switch first terminal coupled to the second switch control terminal, a control terminal coupled to the control signal. The present invention uses leakage inductance manifested by loose coupling between inductors to provide additional control over the switching FETs.